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  1. import sys
  2. sys.dont_write_bytecode = True
  3. ​
  4. from amaranth import *
  5. from amaranth.lib import wiring
  6. from amaranth.lib.wiring import In, Out
  7. from amaranth.lib.enum import Enum
  8. from amaranth.back import verilog
  9. ​
  10. ​
  11. class ALUOp(Enum):
  12. ADD = 0
  13. SUB = 1
  14. SLL = 2
  15. SRA = 3
  16. SRL = 4
  17. AND = 5
  18. OR = 6
  19. XOR = 7
  20. SLT = 8
  21. SLTU = 9
  22. ​
  23. class ALU(wiring.Component):
  24. ​
  25. def __init__(self):
  26. print("### ALU constructor", file=sys.stderr)
  27. super().__init__({
  28. "I_en": In(1),
  29. "I_aluop": In(ALUOp),
  30. "I_op1": In(32),
  31. "I_op2": In(32),
  32. "O_ack": Out(1),
  33. "O_data": Out(32),
  34. "O_eq": Out(1),
  35. "O_neq": Out(1),
  36. "O_lt": Out(1),
  37. "O_ge": Out(1),
  38. "O_ltu": Out(1),
  39. "O_geu": Out(1)
  40. })
  41. ​
  42. def elaborate(self, platform) -> Module:
  43. m = Module()
  44. ​
  45. comb = m.d.comb
  46. sync = m.d.sync
  47. ​
  48. # The 32-bit computation result
  49. result = Signal(32)
  50. ​
  51. ### Shifter signals ###
  52. ​
  53. shift = Signal(1) # shift operation requested?
  54. shift_right = Signal(1) # is a right shift (arithmetic or logical) requested?
  55. shift_signed = Signal(1) # is this an arithmetic shift?
  56. shift_sign = Signal(1) # sign bit to be shifted in on right shifts
  57. shift_finished = Signal(1) # is the multi-cycle shifter finished?
  58. shift_counter = Signal(5) # how many bits to shift
  59. with m.Switch(self.I_aluop):
  60. with m.Case(ALUOp.SLL):
  61. comb += [shift.eq(1), shift_right.eq(0), shift_signed.eq(0)]
  62. with m.Case(ALUOp.SRA):
  63. comb += [shift.eq(1), shift_right.eq(1), shift_signed.eq(1)]
  64. with m.Case(ALUOp.SRL):
  65. comb += [shift.eq(1), shift_right.eq(1), shift_signed.eq(0)]
  66. with m.Default():
  67. comb += [shift.eq(0), shift_right.eq(0), shift_signed.eq(0)]
  69. comb += shift_sign.eq(Mux(shift_signed, self.I_op1[31], 0))
  70. sync += shift_finished.eq(0)
  71. ​
  72. ### Comparison flags stuff ###
  73. # Using a 33-bit subtraction result and a 32-bit xor to compute
  74. # less-than and less-than-unsigned results.
  75. # Given we need sub and xor anyways, this saves logic.
  76. ​
  77. eq = Signal(1)
  78. lt = Signal(1)
  79. ltu = Signal(1)
  80. sub = Signal(33) # 33 bits, additional bit for underflow detection
  81. xor = Signal(32) # 32 bits
  82. ​
  83. comb += {
  84. sub.eq(self.I_op1 - self.I_op2), # Subtraction with 33-bit result
  85. xor.eq(self.I_op1 ^ self.I_op2), # 32-bit xor
  86. eq.eq(self.I_op1 == self.I_op2),
  87. lt.eq(sub[32] ^ xor[31]), # signed comparison: xor underflow bit with xored sign bit
  88. ltu.eq(sub[32]) # unsigned comparison: simply look at underflow bit
  89. }
  90. ​
  91. with m.If(self.I_en):
  92. with m.If(~shift): # Single-cycle OPs
  93. with m.Switch(self.I_aluop):
  94. with m.Case(ALUOp.ADD):
  95. sync += result.eq(self.I_op1 + self.I_op2)
  96. with m.Case(ALUOp.SUB):
  97. sync += result.eq(sub[0:32])
  98. with m.Case(ALUOp.AND):
  99. sync += result.eq(self.I_op1 & self.I_op2)
  100. with m.Case(ALUOp.OR):
  101. sync += result.eq(self.I_op1 | self.I_op2)
  102. with m.Case(ALUOp.XOR):
  103. sync += result.eq(xor)
  104. with m.Case(ALUOp.SLT):
  105. sync += result.eq(Cat(lt, 0))
  106. with m.Case(ALUOp.SLTU):
  107. sync += result.eq(Cat(ltu, 0))
  108. ​
  109. with m.Else(): # Multi-cycle shifts
  110. with m.FSM():
  111. with m.State("shift_idle"):
  112. sync += result.eq(self.I_op1)
  113. sync += shift_counter.eq(self.I_op2)
  114. m.next = "shift_work"
  115. with m.State("shift_work"):
  116. with m.If(shift_counter.bool() & shift):
  117. with m.If(shift_right):
  118. sync += result.eq(Cat(result[1:32], shift_sign))
  119. with m.Else():
  120. sync += result.eq(Cat(0, result[0:31]))
  121. sync += shift_counter.eq(shift_counter - 1)
  122. with m.Else():
  123. sync += shift_finished.eq(1)
  124. m.next = "shift_finish"
  125. with m.State("shift_finish"):
  126. # just hold output for one clock cycle longer
  127. m.next = "shift_idle"
  128. ​
  129. ack = (~shift) | (shift & shift_finished)
  130. ​
  131. # wire output signals
  132. comb += [
  133. self.O_ack.eq(ack),
  134. self.O_data.eq(result),
  135. ]
  136. # register comparison flags
  137. sync += [
  138. self.O_eq.eq(eq),
  139. self.O_neq.eq(~eq),
  140. self.O_lt.eq(lt),
  141. self.O_ge.eq(~lt),
  142. self.O_ltu.eq(ltu),
  143. self.O_geu.eq(~ltu),
  144. ]
  145. ​
  146. return m
  148. ​
  149. if __name__ == "__main__":
  150. ​
  151. alu = ALU()
  152. ​
  153. with open("alu.v", "w") as f:
  154. f.write(verilog.convert(alu))